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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jui-Jen Wu Yen-Huei Chen Meng-Fan Chang Po-Wei Chou Chien-Yuan Chen Hung-Jen Liao Ming-Bin Chen Yuan-Hua Chu Wen-Chin Wu Yamauchi, H. |
| Copyright Year | 1966 |
| Abstract | Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within the same area as the single-ended DS8T. Thanks to D2S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32 Kb macro is 14% smaller area and 53% faster than DS8T cells. Three macros were fabricated using foundry provided 65 nm low-power and 90 nm generic processes. The measured VDDmin for a 65 nm 256-row 32 Kb and a 32-row 4 Kb macro are 430 mV and 250 mV respectively. The measured VDDmin for a 90 nm 256-row 64 Kb macro is 230 mV. |
| Sponsorship | IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE |
| Starting Page | 815 |
| Ending Page | 827 |
| Page Count | 13 |
| File Size | 2796688 |
| File Format | |
| ISSN | 00189200 |
| Volume Number | 46 |
| Issue Number | 4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-04-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Sensors Layout Transistors Logic gates Noise Switches write margin Low supply voltage SRAM read disturb static noise margin |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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