NDLI: Tapered-Vth Approach for Energy-Efficient CMOS Buffers

Content Provider	IEEE Xplore Digital Library
Author	Frustaci, F. Alioto, M. Corsonello, P.
Copyright Year	2004
Abstract	In this paper, “tapered-Vth” buffers are explored as an approach to significantly improve the energy efficiency of traditional CMOS buffers. In this approach, the transistor threshold voltage is progressively increased throughout the buffer stages, in addition to the traditional transistor tapered sizing. Analysis shows that tapered-Vth buffers are able to significantly widen the range of energy-delay trade-offs achievable in real designs, thereby showing improved design flexibility compared to single-Vth buffers. In addition, tapered-Vth buffers are shown to offer an up to 3× energy reduction under a given performance constraint. A circuit-level optimization procedure including the leakage energy contribution is adopted to explore the entire energy-delay space, in contrast to previous analyses that targeted only a specific point. To this aim, an analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort methodology. Simulations in a 45-nm CMOS technology are extensively performed to validate the approach in a case study (Word Lines buffers for memory arrays) and in a number of other design cases. Extensive simulations are performed to understand the limits of the proposed approach, as well as the impact of the activity rate, the supply voltage, and process variations.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2698
Ending Page	2707
Page Count	10
File Size	1002965
File Format	PDF
ISSN	15498328
Volume Number	58
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay CMOS integrated circuits Transistors Threshold voltage Optimization Capacitance Inverters VLSI CMOS buffers digital circuits energy efficient low power low leakage
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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