NDLI: An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links

Content Provider	IEEE Xplore Digital Library
Author	Zamarreno-Ramos, C. Serrano-Gotarredona, T. Linares-Barranco, B.
Copyright Year	2004
Abstract	This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage differential signaling (LVDS) and two handshaking lines. Each event is represented by a 32-bit word. Two extra preamble bits are used for alignment. Transmission clock is embedded in the data using Manchester encoding. As opposed to conventional LVDS links, the presented approach allows to stop physical communication between data events, so that no “comma” characters need to be transmitted during these pauses. As soon as a new event needs to be transmitted, the link recovers immediately thanks to a built-in control voltage memorization circuit. As a result, power consumption of the serializer and deserializer circuits is proportional to data event rate. The approach is also highly tolerant to clock jitter, due to the asynchronous nature and the Manchester encoding. A chip test prototype has been fabricated in standard 0.35 μm CMOS including a pair of Serializer and Deserializer circuits. Maximum measured event transmission rate is 15 Meps (mega events per second) for 32-bit events, with a maximum bit transmission speed of 670 Mbps (mega bits per second).
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2647
Ending Page	2660
Page Count	14
File Size	2068208
File Format	PDF
ISSN	15498328
Volume Number	58
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Receivers Jitter Sensors Synchronization Encoding Very large scale integration serial interchip communication Address event representation (AER) asynchronous circuits asynchronous communications clock data recovery (CDR) event-driven processing low voltage differential signaling (LVDS) Manchester encoding neuromorphic circuits and systems serial AER
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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