NDLI: Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Staszewski, R.B. Waheed, K. Dulger, F. Eliezer, O.E.
Copyright Year	1966
Abstract	We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm² and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2904
Ending Page	2919
Page Count	16
File Size	2073408
File Format	PDF
ISSN	00189200
Volume Number	46
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency modulation Phase locked loops Bandwidth Transfer functions CMOS integrated circuits Converters time-to-digital converter (TDC) All-digital PLL (ADPLL) digitally-controlled oscillator (DCO) dithering multirate signal processing phase-locked loop (PLL)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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