NDLI: An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

Content Provider	IEEE Xplore Digital Library
Author	Kwang-Hee Choi Jung-Bum Shin Jae-Yoon Sim Hong-June Park
Copyright Year	2004
Abstract	A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm² . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2055
Ending Page	2063
Page Count	9
File Size	1351567
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital control Oscillators Phase locked loops Delay Interpolation Frequency measurement Inverters CMOS process Jitter Energy consumption wide range All-digital phase-locked loop (ADPLL) digitally controlled oscillator (DCO) interpolation tri-state inverter
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

A portable digitally controlled oscillator using novel varactors

A Jitter and Power Analysis on DCO

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

Similar Documents

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

A portable digitally controlled oscillator using novel varactors

A Jitter and Power Analysis on DCO

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL