NDLI: An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs

Content Provider	IEEE Xplore Digital Library
Author	Da-Cheng Juan Yu-Ting Chen Ming-Chao Lee Shih-Chieh Chang
Copyright Year	1993
Abstract	During the power mode transition, simultaneously turning on sleep transistors provides a sufficiently large surge current, which may cause a large IR drop in the power networks. The IR drop in turn causes errors in the retention sequential elements of the sleep modules or errors of the nonsleep modules. One efficient way to control the surge current is to schedule the turn-on sequences of sleep transistors. In this paper, we introduce several important properties of the surge current during the power mode transition for the distributed sleep transistor network (DSTN) design, which is a popular power gating design style. Based on these properties, we propose an accurate estimation of the surge current and provide efficient schedules on the DSTN structure. Our methods achieved significantly better results than previous works-on average, 261 times wake-up time reduction and 30% less energy loss during the power mode transition.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	246
Ending Page	255
Page Count	10
File Size	1081673
File Format	PDF
ISSN	10638210
Volume Number	18
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surges Job shop scheduling Circuits Capacitance Turning Energy loss CMOS process Energy consumption Transistors Logic devices schedule Leakage low power multithreshold CMOS (MTCMOS) power gating power mode transition
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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