NDLI: Hierarchical Finite-Element Reduction-Recovery Method for Large-Scale Transient Analysis of High-Speed Integrated Circuits

Content Provider	IEEE Xplore Digital Library
Author	Gan, H. Jiao, D.
Copyright Year	1999
Abstract	This paper proposes a hierarchical finite-element reduction-recovery method for large-scale transient analysis of high-speed integrated circuits. This method rigorously reduces the matrix of a multilayer system of O(N) to that of a single-cell system of O(1) regardless of the original problem size. More important, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. In addition, the reduction preserves the sparsity of the original system matrix. As a result, the matrix factorization cost is reduced to O(1) by the proposed method. The CPU cost at each time step scales linearly with the number of unknowns. The method is applicable to any Manhattan-type integrated circuit embedded in layered dielectric media. Numerical and experimental results demonstrate the performance of the proposed method.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society IEEE Components, Packaging and Manufacturing Technology Society
Starting Page	276
Ending Page	284
Page Count	9
File Size	897993
File Format	PDF
ISSN	15213323
Volume Number	33
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite element methods Large scale integration Transient analysis High speed integrated circuits Sparse matrices Central Processing Unit Gallium nitride Nonhomogeneous media Costs Circuit analysis transient analysis Electromagnetics finite-element method integrated circuits large-scale analysis time domain
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in