NDLI: FPGA Based System for Open, Short, and <emphasis emphasistype=italic>RC</emphasis> Impedance Measurement

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Year : 2010 Volume : 33

Table of contents

IEEE Transactions on Advanced Packaging publication information

Noise Isolation in Mixed-Signal Systems Using Alternating Impedance Electromagnetic Bandgap (AI-EBG) Structure-Based Power Distribution Network (PDN)

Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability

Defect Detection of Flip Chip Solder Bumps With Wavelet Analysis of Laser Ultrasound Signals

Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications

Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications

Analysis of Adhesion and Fracture Energy of Nano-Particle Silver in Electronics Packaging Applications

Recrystallization, Electric Flame-Off Characteristics, and Electron Backscatter Diffraction of Copper Bonding Wires

Reliability Verification of Hermetic Package With Nanoliter Cavity for RF-Micro Device

Fine-Pitch Capabilities of the Flat Ultra-Thin Chip Packaging (UTCP) Technology

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

Rapid Assessment of BGA Fatigue Life Under Vibration Loading

Peridynamic Theory for Thermomechanical Analysis

Design and Analysis of Packaging Boxes for Flat Panel Displays

Parallel Simulation of Massively Coupled Interconnect Networks

Correction of the Method of Images for Partial Inductance Calculations of QFP

Active Heatsink Antenna for Radio-Frequency Transmitter

FPGA Based System for Open, Short, and RC Impedance Measurement

On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements

LTCC Spiral Inductor Synthesis and Optimization With Measurement Verification

Wideband Circuit Model for Planar EBG Structures

Characterization of Next Generation Thin Low-K and Low-Loss Organic Dielectrics From 1 to 110 GHz

Electromigration Characteristic of SnAg $_{3.0}$Cu $_{0.5}$ Flip Chip Interconnection

Electrical Characterization of Screen-Printed Circuits on the Fabric

Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression

Fast Reduced-Order Finite-Element Modeling of Lossy Thin Wires Using Lumped Impedance Elements

Time Domain Delay Extraction-Based Macromodeling Algorithm for Long-Delay Networks

Analysis of Shielded Electromagnetic Bandgap Structures Using Multiconductor Transmission-Line Theory

Delay-Based Macromodeling of Long Interconnects From Frequency-Domain Terminal Responses

Fast Passivity Enforcement for S-Parameter Models by Perturbation of Residue Matrix Eigenvalues

Fast Reduction Algorithms in the Frequency-Domain Layered Finite Element Method for the Electromagnetic Analysis of Large-Scale High-Frequency Integrated Circuits

Hierarchical Finite-Element Reduction-Recovery Method for Large-Scale Transient Analysis of High-Speed Integrated Circuits

The Impact of On-Wafer Calibration Method on the Measured Results of Coplanar Waveguide Circuits

$z$ -Domain Orthonormal Basis Functions for Physical System Identifications

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Table of contents

Table of contents

IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

IEEE Components, Packaging, and Manufacturing Technology Society Information

Year : 2009 Volume : 32

Year : 2008 Volume : 31

Year : 2007 Volume : 30

Year : 2006 Volume : 29

Year : 2005 Volume : 28

Year : 2004 Volume : 27

Year : 2003 Volume : 26

Year : 2002 Volume : 25

Year : 2001 Volume : 24

Year : 2000 Volume : 23

Year : 1999 Volume : 22

FPGA Based System for Open, Short, and RC Impedance Measurement

Content Provider	IEEE Xplore Digital Library
Author	Newman, K.E.
Copyright Year	1999
Abstract	This paper describes a time-based digital test system that may be used to detect opens, and shorts, as well as measure resistive and capacitive impedance of interconnect networks. The specific test implementation is customized through a field programmable gate array (FPGA). The use of an FPGA allows for reconfiguration of the test for many different interconnect verifications. The current progress of this system is demonstrated and experimental measurements are provided.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society IEEE Components, Packaging and Manufacturing Technology Society
Starting Page	147
Ending Page	152
Page Count	6
File Size	657452
File Format	PDF
ISSN	15213323
Volume Number	33
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays System testing Transmitters Impedance measurement Packaging Hardware Monitoring Timing Time measurement Logic testing reconfigurable system Embedded passives interconnect test
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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