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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cabodi, G. Garcia, L.A. Murciano, M. Nocco, S. Quer, S. |
| Copyright Year | 1982 |
| Abstract | Interpolant-based model checking has been shown to be effective on large verification instances, as it efficiently combines automated abstraction and reachability fixed-point checks. On the other hand, methods based on variable quantification have proved their ability to remove free inputs, thus projecting the search space over state variables. In this paper, we propose an integrated approach which combines the abstraction power of interpolation with techniques that rely on and-inverter graph (AIG) and/or binary decision diagram (BDD) representations of states, directly supporting variable quantification and fixed-point checks. The underlying idea of this combination is to adopt AIG or BDD-based quantifications to limit and restrict the search space and the complexity of the interpolant-based approach. The exploited strategies, most of which are individually well known, are integrated with a new flavor, specifically designed to improve their effectiveness on difficult verification instances. Experimental results, specifically oriented to hard-to-solve verification problems, show the robustness of our approach. |
| Sponsorship | IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society |
| Starting Page | 382 |
| Ending Page | 395 |
| Page Count | 14 |
| File Size | 710790 |
| File Format | |
| ISSN | 02780070 |
| Volume Number | 29 |
| Issue Number | 3 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuits Interpolation Data structures Boolean functions Formal verification Binary decision diagrams Robustness Hardware Concrete Logic symbolic techniques formal methods formal verification model checking satisfiability |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software |
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