NDLI: Analysis of Clock Jitter in Continuous-Time Sigma

Content Provider	IEEE Xplore Digital Library
Author	Vasudevan, V.
Copyright Year	2004
Abstract	One of the factors limiting the performance of continuous-time sigma-delta modulators (CTSDMs) is clock jitter. This jitter can be classified as synchronous and accumulated/long-term jitter. A clock that is derived from a phase-lock loop contains both types of jitter. In this paper, we present a framework that can be used to obtain the output spectrum in the presence of jitter, either synchronous or accumulated or a combination of both. First, a general expression for the output power spectral density (PSD) of the CTSDM in the presence of clock jitter is derived. Based on this, analytical expressions for the output PSD are obtained for particular cases of synchronous and long-term jitter. These are validated against behavioral simulations.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	519
Ending Page	528
Page Count	10
File Size	347799
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Genetic expression Power generation Impedance matching Analytical models Timing jitter Digital-analog conversion Performance analysis Feedback sigma–delta modulator Clock jitter
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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