NDLI: Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

Content Provider	IEEE Xplore Digital Library
Author	Sundstrom, T. Murmann, B. Svensson, C.
Copyright Year	2004
Abstract	A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	509
Ending Page	518
Page Count	10
File Size	564007
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Analog-digital conversion Sampling methods Digital systems Pipelines Error correction CMOS analog integrated circuits High-speed electronics Power demand CMOS technology power demand Analog–digital conversion high-speed electronics
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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