NDLI: Efficient Multibit Quantization in Continuous-Time <formula formulatype=inline> <tex>$Sigma Delta$</tex></formula> Modulators

Content Provider	IEEE Xplore Digital Library
Author	De Maeyer, J. Rombouts, P. Weyten, L.
Copyright Year	2004
Abstract	A drawback of continuous-time SigmaDelta modulators is their sensitivity to clock jitter. One way to counteract this is to use a multibit feedback loop which requires a (high resolution) multibit quantizer. However, every extra bit in the quantizer doubles its complexity, power consumption and capacitive load for the analog circuit that needs to drive the quantizer. In this paper a new concept for the quantization in sigma delta modulators is proposed. It allows to significantly reduce the required amount of comparators in the multibit quantizer. Three architectures that realize this new concept are presented and their implementation issues discussed. The architectures' performance has been compared with a conventional modulator through computer simulations. Compared to the conventional modulator, the proposed architectures achieve the same performance, with much less comparators in the quantizer
Sponsorship	IEEE Circuits and Systems Society
Starting Page	757
Ending Page	767
Page Count	11
File Size	715670
File Format	PDF
ISSN	15498328
Volume Number	54
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Quantization Delta-sigma modulation Computer architecture Clocks Jitter Feedback loop Energy consumption Analog circuits Delta modulation Computer simulation sigma–delta ($\Sigma \Delta$ ) modulation Analog-to-digital conversion quanitzation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter

Comments on Efficient Multibit Quantization in Continuous-Time $Sigma Delta$ Modulators

Analysis of Clock-Jitter Effects in Continuous-Time $Delta Sigma $ Modulators Using Discrete-Time Models

General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators

Analysis of Clock Jitter in Continuous-Time Sigma–Delta Modulators

Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

Efficient Multibit Quantization in Continuous-Time $Sigma Delta$ Modulators

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