NDLI: An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Content Provider	IEEE Xplore Digital Library
Author	Jaehoon Song Hyunbean Yi Juhee Han Sungju Park
Copyright Year	2004
Abstract	Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	554
Ending Page	565
Page Count	12
File Size	1735034
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bridges System-on-a-chip Automatic testing Costs System testing Time to market Manufacturing Protocols Microcontrollers Silicon testability Advanced microcontroller bus architecture (AMBA) bus bridge peripheral component interconnect (PCI) system-on-a-chip (SoC) test time
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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