NDLI: A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

Content Provider	IEEE Xplore Digital Library
Author	Limotyrakis, S. Kulchycki, S.D. Su, D.K. Wooley, B.A.
Copyright Year	1966
Abstract	A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-/spl mu/m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1057
Ending Page	1067
Page Count	11
File Size	926377
File Format	PDF
ISSN	00189200
Volume Number	40
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines CMOS technology Analog-digital conversion Circuits Operational amplifiers Power amplifiers Prototypes Sampling methods Frequency Power dissipation switched-capacitor circuits Analog–digital (A/D) conversion CMOS analog integrated circuits comparators folding A/D converters mixed analog–digital integrated circuits operational amplifiers pipeline processing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

Digital calibration for monotonic pipelined A/D converters

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A Power Efficient 12-bit and 25-MS/s Pipelined ADC for the ILC/Ecal Integrated Readout

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

Similar Documents

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

Digital calibration for monotonic pipelined A/D converters

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A Power Efficient 12-bit and 25-MS/s Pipelined ADC for the ILC/Ecal Integrated Readout

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling

A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC