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  1. Embedded Systems Letters
  2. Year : 2009 Volume : 1
  3. Issue 2
  4. A Layer-Multiplexed 3D On-Chip Network Architecture
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Year : 2015 Volume : 7
Year : 2014 Volume : 6
Year : 2013 Volume : 5
Year : 2012 Volume : 4
Year : 2011 Volume : 3
Year : 2010 Volume : 2
Year : 2009 Volume : 1
Issue 4
Issue 3
Issue 2
Table of contents
IEEE Embedded Systems Letters publication information
Temperature Compensated Time Synchronization
Embedded Software Design of Scalable Low-Area Elliptic-Curve Cryptography
SCoPE: Towards a Systolic Array for SVM Object Detection
A Layer-Multiplexed 3D On-Chip Network Architecture
BOUNCE: A New High-Resolution Time-Interval Measurement Architecture
IEEE Embedded Systems Letters
The Cyber-Physical Systems Week 2010 (CPSWEEK 2010)
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IEEE Embedded Systems Letters Information for authors
Blank page [back cover]
Issue 1

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A Layer-Multiplexed 3D On-Chip Network Architecture

Content Provider IEEE Xplore Digital Library
Author Sunkam Ramanujam, R. Lin, B.
Copyright Year 2009
Abstract Programmable many-core processors are poised to become a major design option for many embedded applications. In the design of power-efficient embedded many-core processors, the architecture of the on-chip network plays a central role. Many designs have relied on a 2D mesh architecture as the underlying communication fabric. With the emergence of 3D technology, new on-chip network architectures are possible. In this paper, we propose a novel layer-multiplexed (LM) 3D network architecture that takes advantage of the short interlayer wiring delays enabled in 3D technology. In particular, the LM architecture replaces the one-layer-per-hop routing in a conventional 3D mesh with simpler vertical demultiplexing and multiplexing structures. When combined with a layer load-balanced oblivious routing algorithm, it can achieve the same worst-case throughput as the best known oblivious routing algorithm on a conventional 3D mesh. However, in comparison to a conventional 3D mesh, the LM architecture consumes 27% less power, attains 14.5% higher average throughput, and achieves 33% lower worst-case hop count on a 4 times 4 times 4 topology.
Starting Page 50
Ending Page 55
Page Count 6
File Size 281182
File Format PDF
ISSN 19430663
Volume Number 1
Issue Number 2
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2009-08-01
Publisher Place U.S.A.
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Network-on-a-chip Routing Throughput Fabrics Wiring Application specific integrated circuits Delay Mesh networks Embedded system System-on-a-chip integrated circuits (ICs) 3D 3D mesh oblivious routing
Content Type Text
Resource Type Article
Subject Control and Systems Engineering Computer Science
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