NDLI: Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Content Provider	IEEE Xplore Digital Library
Author	Tasdizen, O. Akin, A. Kukner, H. Hamzaoglu, I.
Copyright Year	1975
Abstract	Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition (HD) video formats, the computational complexity of full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, in this paper, we present dynamically variable step search (DVSS) ME algorithm for processing high definition video formats and a dynamically reconfigurable hardware architecture for efficiently implementing DVSS algorithm. The simulation results showed that DVSS algorithm performs very close to FS algorithm by searching much fewer search locations than FS algorithm and it outperforms successful fast search ME algorithms by searching more search locations than these algorithms. The proposed hardware is implemented in VHDL and is capable of processing high definition video formats in real time. Therefore, it can be used in consumer electronics products for video compression, frame rate up-conversion and de-interlacing.
Sponsorship	IEEE Consumer Electronics Society
File Size	414505
File Format	PDF
ISSN	00983063
Volume Number	55
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Motion estimation Heuristic algorithms Hardware Video compression High definition video Videoconference Consumer electronics Computational complexity PSNR Computer architecture FPGA Motion Estimation Video Compression Video Enhancement Hardware Implementation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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