NDLI: FIR filter design methodology for hardware optimized implementation

Content Provider	IEEE Xplore Digital Library
Author	Mehboob, R. Khan, S.A. Qamar, R.
Copyright Year	1975
Abstract	This paper presents a novel method of FIR filter design for optimized hardware implementation. The FIR filters are extensively employed in a variety of consumer devices like TVs, mobile phones and docking stations. The optimized implementations of FIR filter furnish high quality signal processing at reasonable cost. The paper first analyzes the effects of quantization on frequency response of a filter by successively reducing the number of bits in each coefficient. Empirical analysis of coefficient quantization reveals a relationship between the number of bits, number of coefficients and the frequency response. The paper then presents a methodology for an optimized design of an FIR filter for hardware implementation. The proposed approach first designs a filter with certain parameters and then redesigns the same filter with tighter constraints resulting in higher filter order. The coefficients of the improved or over designed filter are then quantized successively with lesser number of bits by an iterative algorithm to a level where its frequency response matches to the original requirements. The synthesis results show that a significant reduction in hardware resources can be achieved using this methodology. The proposed approach has so far not been reported for reduction in hardware resources.
Sponsorship	IEEE Consumer Electronics Society
File Size	278670
File Format	PDF
ISSN	00983063
Volume Number	55
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Design methodology Hardware Design optimization Frequency response Quantization Mobile handsets Signal processing Cost function Algorithm design and analysis FIR Filter and Hardware Resources Bit Length Optimization
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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