NDLI: An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates

Content Provider	IEEE Xplore Digital Library
Author	Martorell, F. Cotofana, S.D. Rubio, A.
Copyright Year	2002
Abstract	The predicted deterioration of the component quality, due to the shrinking of components to near atomic scale, threatens the effectiveness and the applicability of conventional digital system design methodologies in the giga and tera-scale integration era. Three aggression sources support the previous statement: i) the increasing device parameter variability induced by the extreme reduction of the critical feature sizes and the intrinsic nature of new devices; ii) the intense and practically unpredictable internal noise; and iii) the large number of physical defects. This paper provides a detailed analysis of the noise and parameter variations effects on a basic processing gate. We derive formulas to calculate the expected value and the variance of the gate output under the effects of noise, threshold, and gain fluctuations. Using these expressions we also derive a cost-performance equation that evaluates the gate error probability from its parameter variability, noise, power, and area or redundance. The proposed model is generic for any computing gate in the current digital paradigm. To illustrate the model applicability we calculate the error probability curve for a 90 nm CMOS inverter showing that for this technology the noise is the main limiting factor. A tradeoff analysis of area-power-redundancy-reliability for nanogates is performed indicating that the use of nanoscale individual elements for fabricating gates in deep-nanoscale technologies may not be a viable option. The results clearly suggest that the use of redundant structures is necessary and that averaging structures with mid-high redundancy factors may constitute a reasonable solution for building reliable nanoscale gates.
Sponsorship	IEEE Nanotechnology Council
Starting Page	24
Ending Page	33
Page Count	10
File Size	860295
File Format	PDF
ISSN	1536125X
Volume Number	7
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error probability Semiconductor device modeling CMOS technology Digital systems Design methodology Noise reduction Fluctuations Equations Inverters Performance analysis nonlinear functions Fault tolerance logic design nanotechnology non-linear functions
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Efficient Timing Model for CMOS Combinational Logic Gates

Inverter models of CMOS gates for supply current and delay evaluation

Exploring Fine-Grained Fault Tolerance for Nanotechnology Devices With the Recursive NanoBox Processor Grid

Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories

Physical design guides for substrate noise reduction in CMOS digital circuits

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

Delay analysis of CMOS gates using modified logical effort model

A new methodology for design of BiCMOS gates and comparison with CMOS

An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates

Similar Documents

An Efficient Timing Model for CMOS Combinational Logic Gates

Inverter models of CMOS gates for supply current and delay evaluation

Exploring Fine-Grained Fault Tolerance for Nanotechnology Devices With the Recursive NanoBox Processor Grid

Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories

Physical design guides for substrate noise reduction in CMOS digital circuits

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

Delay analysis of CMOS gates using modified logical effort model

A new methodology for design of BiCMOS gates and comparison with CMOS

An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates