NDLI: On the Reliability of Majority Gates Full Adders

Content Provider	IEEE Xplore Digital Library
Author	Ibrahim, W. Beiu, V. Sulieman, M.H.
Copyright Year	2002
Abstract	This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that of a standard XOR-based FA. The analysis provides insights into different parameters that affect the reliability of FAs. The probability transfer matrix method is used to exactly calculate the reliability of the FAs under investigation. All simulation results show that majority gates FAs are more robust than a standard XOR-based FA. They also show how different gates affect the FAs' reliabilities and are extrapolated to give reliability estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).
Sponsorship	IEEE Nanotechnology Council
Starting Page	56
Ending Page	67
Page Count	12
File Size	1121143
File Format	PDF
ISSN	1536125X
Volume Number	7
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Birth disorders Adders Energy consumption Electronics industry Solid state circuits Probability Robustness Digital arithmetic Digital signal processors reliability Full adders majority gates probability of failure probability transfer matrix
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

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