NDLI: Inverter models of CMOS gates for supply current and delay evaluation

Content Provider	IEEE Xplore Digital Library
Author	Nabavi-Lishi, A. Rumin, N.C.
Copyright Year	1982
Abstract	The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well.<>
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1271
Ending Page	1279
Page Count	9
File Size	907637
File Format	PDF
ISSN	02780070
Volume Number	13
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Current supplies Delay CMOS logic circuits Logic gates Timing CMOS digital integrated circuits Pulse inverters Digital circuits Voltage
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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