NDLI: An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput

Content Provider	IEEE Xplore Digital Library
Author	Chiper, D.-F. Swamy, M.N.S. Ahmad, M.O.
Copyright Year	1991
Abstract	In this paper, a unified design framework for prime-length forward and inverse discrete cosine transforms with a high throughput is presented. The proposed design facilitates trade-off between the throughput and hardware cost or power consumption, and is well suited for low-power applications. The VLSI structure is highly regular and modular with a topology well suited for the VLSI implementation. The proposed approach is based on the derivation of new efficient systolic algorithms. The algorithms have the same core structure for both the transforms, and the core structure consists of two circular correlations, which unlike other similar computational structures, have the same length and form. Thus, they can be computed in parallel and mapped on the same linear systolic array with channels having a low I/O bandwidth requirement and their number being independent of the transform length N. Further, it is shown that the two transforms, can be efficiently implemented on the same VLSI chip, where only the pre- and post-processing stages are different. The proposed systolic algorithms retain the benefits provided by VLSI implementations based on circular or cyclic convolution structures, and at the same time has a simpler control structure, high speed and low complexity
Sponsorship	IEEE Signal Processing Society
Starting Page	2925
Ending Page	2936
Page Count	12
File Size	623090
File Format	PDF
ISSN	1053587X
Volume Number	55
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Throughput Very large scale integration Hardware Costs Energy consumption Topology Concurrent computing Systolic arrays Bandwidth VLSI algorithms Discrete cosine transform (DCT) high throughput implementation systolic arrays unified DCT/IDCT structure
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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