NDLI: New systolic array implementation of the 2-D discrete cosine transform and its inverse

Content Provider	IEEE Xplore Digital Library
Author	Yu-Tai Chang Chin-Liang Wang
Copyright Year	1991
Abstract	A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N/sup 2/ multipliers to evaluate N/spl times/N-point DCTs at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required.<>
Sponsorship	IEEE Circuits and Systems Society
Starting Page	150
Ending Page	157
Page Count	8
File Size	767841
File Format	PDF
ISSN	10518215
Volume Number	5
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Systolic arrays Discrete cosine transforms Throughput Matrix decomposition Hardware Two dimensional displays Computer architecture Discrete transforms Clocks Very large scale integration
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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