NDLI: Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

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Lateral Scale Down of InGaAs/InAs Composite-Channel HEMTs With Tungsten-Based Tiered Ohmic Structure for 2-S/mm $g_{m}$ and 500-GHz $f_{T}$

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RF, DC, and Reliability Performance of MIM Capacitors Embedded in Organic Substrates by Wafer-Transfer Technology (WTT) for System-on-Package Applications

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Highly Reliable 1.5-${rm mu}hbox{m}$ DFB Laser With High-Mesa SIBH Structure

$V_{T}$ Compensation Circuit for AM OLED Displays Composed of Two TFTs and One Capacitor

Design and Characterization of CMOS/SOI Image Sensors

Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on Bias Temperature Instability and Gate Dielectric Breakdown of HfSiON MOSFETs

Analytic Charge Model for Surrounding-Gate MOSFETs

High-$kappa$ Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality—A Mobility Study

An Investigation of Negative Differential Resistance and Novel Collector–Current Kink Effects in SiGe HBTs Operating at Cryogenic Temperatures

Prototype of Phase-Change Channel Transistor for Both Nonvolatile Memory and Current Control

SILC and NBTI in pMOSFETs With Ultrathin SiON Gate Dielectrics

Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate

Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

An Analytical Model of Electric Substrate Losses for Planar Spiral Inductors on Silicon

Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insu lator (SGOI) MOSFETs

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs

Modeling and Characterization of Effects of Dummy-Gate Bias on LDMOSFETs

Epitaxial Design of a Direct Optically Controlled GaAs/AlGaAs-Based Heterostructure Lateral Superjunction Power Device for Fast Repetitive Switching

Aperture-Collimated Double-Gated Silicon Field Emitter Arrays

A High-Performance Micromachined RF Monolithic Transformer With Optimized Pattern Ground Shields (OPGS) for UWB RFIC Applications

Simulation Results for Nanoscale Field Effect Diode

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Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

Content Provider	IEEE Xplore Digital Library
Author	Palumbo, D. Masala, S. Tassini, P. Rubino, A. della Sala, D.
Copyright Year	1963
Abstract	This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the fabrication and with small grains dimension. With the aid of numerical simulations, we investigate the effects of static stress using two types of procedures: the on stress and the hot carrier stress. Results show that the variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsible for the degradation of TFTs performances in both the two types of stress and that the interface trap states play a negligible role compared to the bulk trap states
Sponsorship	IEEE Electron Devices Society
Starting Page	476
Ending Page	482
Page Count	7
File Size	420628
File Format	PDF
ISSN	00189383
Volume Number	54
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	thin-film transistor (TFTs) Density-of-states (DoS) fixed charge numerical simulation reliability
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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