NDLI: Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

Content Provider	IEEE Xplore Digital Library
Author	Yu, S. Petranovic, D.M. Krishnan, S. Kwyro Lee Yang, C.Y.
Copyright Year	1963
Abstract	An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.
Sponsorship	IEEE Electron Devices Society
Starting Page	135
Ending Page	145
Page Count	11
File Size	1030398
File Format	PDF
ISSN	00189383
Volume Number	53
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections CMOS integrated circuits Integrated circuit modeling Linear circuits Resistance modeling Electromagnetic coupling inductance integrated circuit interconnections
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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