NDLI: An effective single-trap-level model for the proton-induced semi-insulating substrates

Content Provider	IEEE Xplore Digital Library
Author	Chungpin Liao Jeng-Shin Hsu
Copyright Year	1963
Abstract	To suppress the undesirable substrate couplings, a novel approach, called the /spl pi/ technology (particle-enhanced isolation), was previously proposed, in which energetic proton beams were applied on the already-manufactured mixed-mode IC wafers prior to their packaging . The results of an improvement of 25-30 dB in coupling reduction and a two-to-three folds enhancement in inductor Q values were also demonstrated. The continuing improvement of this /spl pi/ technology has shed light on the concept of a new very large-scale integration backend solution: the particle-beam stand, a brute-force that may ultimately bring general system-on-a-chip manufacturing to a common platform. However, up to this day the physics describing properties of such proton-caused defect phase has never emerged. In this paper, the possible establishment of an effective, self-consistent, single level defect model is attempted. It will be carried out by fitting the existing single-trap-level theory with experimentally obtained parameters and the data from numerical simulations using the the stopping and range of ions in matter code (a charged-particle stopping-power calculation program). It will be revealed that, more than mere simple traps of charge carriers, those proton-created defects were also intrinsically charged (carrying +e or -e) and thus all were participating in the Rutherford-like scattering of the remaining free charge carriers which had survived the defect trapping. The calculated effective single trap level (E/sub T/) is about +0.24 eV in n-Si and -0.34 eV in p-Si, measuring from the center of the energy bandgap.
Sponsorship	IEEE Electron Devices Society
Starting Page	83
Ending Page	88
Page Count	6
File Size	273871
File Format	PDF
ISSN	00189383
Volume Number	53
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mixed analog-digital integrated circuits Isolation technology Very-large-scale integration Integrated circuit manufacture Integrated circuit modeling Particle scattering system-on-a-chip (SOC) Charge trap high- mixed-mode semi-insulating silicon
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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