NDLI: High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

Content Provider	IEEE Xplore Digital Library
Author	Vashchenko, V.A. Concannon, A. ter Beek, M. Hopper, P.
Copyright Year	2001
Abstract	This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is implemented by the creation of a voltage drop using embedded circuit elements. The final clamp voltage is tuned to exceed the power supply level, thus eliminating the potential for latchup. The design is validated by ESD pulse measurements performed on test structures with cascoded, triggered LVTSCRs for 5.5-V tolerant I/O pins in an 0.18-/spl mu/m CMOS process. The results of the first part of the study were used to propose another design for the LVTSCR with a high holding voltage based on emitter area reduction. The proposed device is validated using three-dimensional simulations and experimental analysis.
Sponsorship	IEEE Electron Devices Society IEEE Reliability Society
Starting Page	273
Ending Page	280
Page Count	8
File Size	956499
File Format	PDF
ISSN	15304388
Volume Number	4
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharge Protection Clamps Negative feedback Voltage control Feedback circuits Power supplies Pulse measurements Performance evaluation Circuit testing
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Safety, Risk, Reliability and Quality Electrical and Electronic Engineering

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