NDLI: Correlations of MOSFET transconductance: Its physical origins and relevance to analog MOSFET modeling and operation

Content Provider	IEEE Xplore Digital Library
Author	Zhijiong Luo Shapira, S. Stiles, K.
Copyright Year	1963
Abstract	The correlations of MOSFET transconductance across the full operating regime were studied on a statistically significant number of devices. This is to our knowledge the first time such a measurement is reported. We present "device operation phase diagrams" summarizing our findings: there are only a few, typically two, highly intracorrelated regions of the transconductances in the V/sub g/ - V/sub d/ plane. The diagrams aid analog design by clearly depicting the relative process induced variations of the transconductance between any two operating points. Though crucial for analog design, this correlation structure is not typically captured, nor to our knowledge understood, by circuit design and modeling methodologies. The results also suggest that in order to track, at production, the transconductance process induced variations in the full MOSFET operating regime, it is sufficient to select only a few operating points, sampling each intracorrelated region. Finally, a simple, physics based picture is presented, tracing the origin of the correlation patterns back to the variations of a few physical process parameters common to all modern technologies. We can therefore predict our observations are general, and will extend beyond the 0.25-/spl mu/m technology we examined.
Sponsorship	IEEE Electron Devices Society
Starting Page	853
Ending Page	858
Page Count	6
File Size	1524792
File Format	PDF
ISSN	00189383
Volume Number	50
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs CMOS analog integrated circuits Integrated circuit design Correlation Admittance Semiconductor device modeling
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

MOSFET modeling for RF IC design

CMOS analog integrated circuits based on weak inversion operations

Modeling random telegraph noise under switched bias conditions using cyclostationary RTS noise

Device optimization for digital subthreshold logic operation

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs

Design and Analysis of UHF Micropower CMOS DTMOST Rectifiers

Fully-depleted SOI CMOS for analog applications

Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology

Correlations of MOSFET transconductance: Its physical origins and relevance to analog MOSFET modeling and operation

Similar Documents

MOSFET modeling for RF IC design

CMOS analog integrated circuits based on weak inversion operations

Modeling random telegraph noise under switched bias conditions using cyclostationary RTS noise

Device optimization for digital subthreshold logic operation

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs

Design and Analysis of UHF Micropower CMOS DTMOST Rectifiers

Fully-depleted SOI CMOS for analog applications

Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology

Correlations of MOSFET transconductance: Its physical origins and relevance to analog MOSFET modeling and operation