NDLI: A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

Content Provider	IEEE Xplore Digital Library
Author	Tanzawa, T. Umezawa, A. Taura, T. Shiga, H. Hara, T. Takano, Y. Miyaba, T. Tokiwa, N. Watanabe, K. Watanabe, H. Masuda, K. Naruke, K. Kato, H. Atsumi, S.
Copyright Year	1966
Abstract	The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1485
Ending Page	1492
Page Count	8
File Size	849168
File Format	PDF
ISSN	00189200
Volume Number	37
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flash memory Voltage control CMOS technology Power supplies Flash memory cells CMOS process Microelectronics Decoding Size control
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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