NDLI: A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

Content Provider	IEEE Xplore Digital Library
Author	Kirihata, T. Gall, M. Hosokawa, K. Dortu, J.-M. Hing Wong Pfefferi, P. Ji, B.L. Weinfurtner, O. DeBrosse, J.K. Terletzki, H. Selz, M. Ellis, W. Wordeman, M.R. Kiehl, O.
Copyright Year	1966
Abstract	A 220-mm/sup 2/, 256-Mb SDRAM has been fabricated in fully planarized 0.22-/spl mu/m CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-/spl mu/m WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC/sub 4/ current to /spl sim/90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to /spl sim/1400 faults/chip with only 8% chip overhead.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1711
Ending Page	1719
Page Count	9
File Size	189345
File Format	PDF
ISSN	00189200
Volume Number	33
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SDRAM Random access memory Decoding Solid state circuit design CMOS technology Testing Redundancy Pipelines Frequency Logic arrays
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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