NDLI: High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

Content Provider	IEEE Xplore Digital Library
Author	June Lee Heung-Soo Im Dae-Seok Byeon Kyeong-Han Lee Dong-Hyuk Chae Kyong-Hwa Lee Sang Won Hwang Sung-Soo Lee Young-Ho Lim Jae-Duk Lee Jung-Dal Choi Young-Il Seo Jong-Sik Lee Kang-Deog Suh
Copyright Year	1966
Abstract	A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1502
Ending Page	1509
Page Count	8
File Size	713626
File Format	PDF
ISSN	00189200
Volume Number	37
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Charge pumps Throughput CMOS process Decoding Nonvolatile memory Image storage Voltage Integrated circuit measurements CMOS memory circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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