NDLI: In-situ stress state measurements during chip-on-board assembly

Content Provider	IEEE Xplore Digital Library
Author	Zou, Y. Suhling, J.C. Johnson, R.W. Jaeger, R.C. Mian, A.K.M.
Copyright Year	1999
Abstract	In this work, die stresses in wire bonded chip-on-board (COB) packages have been measured using special [111] silicon stress test chips. The test die incorporate an array of optimized eight-element dual polarity piezoresistive sensor rosettes, which are uniquely capable of evaluating the complete stress state (six stress components) at points on the surface of the die. Sensor resistance measurements were recorded before packaging, after die attachment, and throughout the encapsulant cure process. Using the appropriate theoretical equations, the stresses at sites on the die surface have been calculated from the raw sensor resistance data. Also, three-dimensional (3-D) nonlinear finite element simulations of the chip-on-board packages were performed, and the stress predictions were correlated with the experimental test chip data.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society International Microelectronics Assembly and Packaging Society (IMAPS)
Starting Page	38
Ending Page	52
Page Count	15
File Size	5435757
File Format	PDF
ISSN	1521334X
Volume Number	22
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-01-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress measurement Semiconductor device measurement Assembly Packaging Testing Sensor arrays Surface resistance Electrical resistance measurement Wire Bonding
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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