NDLI: 0.2-/spl mu/m fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

Content Provider	IEEE Xplore Digital Library
Author	Wada, S. Tokushima, M. Fukaishi, M. Matsuno, N. Yano, H. Hida, H. Maeda, T.
Copyright Year	1963
Abstract	This paper reports on new fully-self-aligned gate technology for 0.2-/spl mu/m, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C/sub f//sup rext/) of conventional Y-shaped gate HJFET's. The 0.2-/spl mu/m Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO/sub 2/ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-/spl mu/m gate n-Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.2/Ga/sub 0.8/As HJFET shows very small current saturation voltage of 0.25 V, marked gm/sub max/ of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f/sub T/=71 GHz and f/sub max/=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C/sub f//sup rext/. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's.
Sponsorship	IEEE Electron Devices Society
Starting Page	1656
Ending Page	1662
Page Count	7
File Size	264961
File Format	PDF
ISSN	00189383
Volume Number	45
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lithography Threshold voltage Capacitance Anisotropic magnetoresistance Electron beams Sputtering Breakdown voltage Passivation Analog integrated circuits High speed integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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