NDLI: Gate engineering for deep-submicron CMOS transistors

Content Provider	IEEE Xplore Digital Library
Author	Bin Yu Dong-Hyuk Ju Wen-Chin Lee Kepler, N. Tsu-Jae King Chenming Hu
Copyright Year	1963
Abstract	Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET' I-V characteristics, MOS capacitor quasi-static C-V curves, SIMS profiles, gate sheet resistance, and oxide Q/sub bd/ are compared for different nitrogen implant conditions. A nitrogen dose of 5/spl times/10/sup 15/ cm/sup -2/ is found to be the optimum choice at an implant energy of 40 keV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p/sup +/ gate p-MOSFET and n/sup +/ gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si/sub 1-x/Ge/sub x/ is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active-dopant concentration near the gate/SiO/sub 2/ interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si/sub 1-x/Ge/sub x/ is gate is compared with polysilicon gate in this study.
Sponsorship	IEEE Electron Devices Society
Starting Page	1253
Ending Page	1262
Page Count	10
File Size	368983
File Format	PDF
ISSN	00189383
Volume Number	45
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nitrogen Reliability engineering Boron CMOSFETs MOSFET circuits Transistors Implants MOS capacitors Capacitance-voltage characteristics Degradation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Impact of boron penetration at P/sup +/-poly/gate oxide interface on deep-submicron device reliability for dual-gate CMOS technologies

Oxynitride gate dielectrics for p/sup +/-polysilicon gate MOS devices

Nitridation of the stacked poly-Si gate to suppress the boron penetration in pMOS

Thin polyoxide on the top of poly-Si gate to suppress boron penetration for pMOS

Highly suppressed boron penetration in NO-nitrided SiO/sub 2/ for p/sup +/-polysilicon gated MOS device applications

Effects of source/drain implants on short-channel MOSFET I-V and C-V characteristics

CMOS active pixel image sensor with simple floating gate pixels

Hot-electron hardened Si-gate MOSFET utilizing F implantation

Gate engineering for deep-submicron CMOS transistors

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