NDLI: SRAM bitmap shape recognition and sorting using neural networks

Content Provider	IEEE Xplore Digital Library
Author	Collica, R.S. Card, J.P. Martin, W.
Copyright Year	1988
Abstract	This paper details the use of neural network technologies in the characterization of bit fail patterns occurring on SRAM chips as an alternative to the more traditional rule-based or knowledge-based approach to fail-pattern occurrence and classification analysis. The results of bit fail pattern count analyses are used both for fault analysis post-processing and manufacturing yield improvement methodologies. The move toward neural network implementation comes in response to prohibitively long processing times required for implementation of rule-based algorithms on more complex devices and the added flexibility of a neural network to learn new fail types in a more adaptive mode. An unsupervised approach to fail pattern identification was implemented on a 128 K SRAM chip using a two-layer Kohonen Self Organizing Map for identification and concurrence of bit fail pattern categories within SRAM chips. A second network utilized a multilayer perceptron (MLP) architecture with backpropagation of error for prediction of the number of occurrences per bitmap of each of the 34 previously identified shape types. The MLP used the output of a SOM as its input vector to assist in the feature extraction by shape type. Both trained networks out-performed existing rule-based algorithms both in ability to identify bit fail pattern types, frequency counts, and speed of processing.<>
Sponsorship	IEEE Electron Devices Society IEEE Components, Packaging, and Manufacturing Technology Society IEEE Reliability Society IEEE Solid-State Circuits Society
Starting Page	326
Ending Page	332
Page Count	7
File Size	803709
File Format	PDF
ISSN	08946507
Volume Number	8
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Shape Sorting Neural networks SRAM chips Failure analysis Pattern analysis Manufacturing Organizing Multilayer perceptrons
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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