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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Peicheng Ju Suyama, K. Ferguson Jr., P.F. Wai Lee |
| Copyright Year | 1966 |
| Abstract | A time- and capacitor-multiplexing technique for use in a highly linear switched-capacitor multibit DAC in sigma-delta data converters is presented. The technique uses subintervals in the sample clock to deliver multiple charge packets to holding capacitors. It avoids distortion effects caused by mismatched capacitors and finite opamp gain. A five-level switched-capacitor DAC using the proposed technique was designed as part of an audio-band multibit sigma-delta D/A converter that achieved a dynamic range of 92 dB and a THD of -93 dB with a low oversampling ratio of 32. No trimming, calibration, or dynamic matching scheme was required. The five-level SC DAC has been fabricated in a 2-/spl mu/m CMOS process, and testing confirmed the anticipated theoretical results. |
| Sponsorship | IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE |
| Starting Page | 1316 |
| Ending Page | 1325 |
| Page Count | 10 |
| File Size | 1241416 |
| File Format | |
| ISSN | 00189200 |
| Volume Number | 30 |
| Issue Number | 12 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-12-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delta-sigma modulation Switching converters Dynamic range Quantization Semiconductor device noise Linearity Circuits Analog-digital conversion Capacitors Calibration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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