NDLI: SOI design for competitive CMOS VLSI

Content Provider	IEEE Xplore Digital Library
Author	Fossum, J.G. Choi, J.-Y. Sundaresan, R.
Copyright Year	1963
Abstract	Device simulations using a physical SOI MOSFET model implemented in SPICE2 predict that properly designed silicon-on-insulator (SOI) has a substantial advantage over bulk CMOS VLSI with regard to hot-carrier-induced degradation. The simulations show that the (short-) n-channel SOI MOSFET, designed with moderately thin (not ultrathin) film having complete depletion in the film and at the back surface, and without an LDD region, will degrade much more slowly than a contemporary bulk MOSFET with an LDD. This suggests that the 5-V source can be retained for submicrometer SOI CMOS, whereas it must be lowered for bulk CMOS. The simulations and the optimal SOI designs they suggest are supported by measurements of thin-film and bulklike MOSFETs fabricated in SIMOX SOI.<>
Sponsorship	IEEE Electron Devices Society
Starting Page	724
Ending Page	729
Page Count	6
File Size	703117
File Format	PDF
ISSN	00189383
Volume Number	37
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration MOSFET circuits Degradation CMOS technology Silicon on insulator technology Predictive models Semiconductor device modeling Hot carriers Isolation technology Transistors
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits

Short-channel effects in SOI MOSFETs

A method for the prediction of hot-carrier lifetime in floating SOI NMOSFETs

Model selection for SOI MOSFET circuit simulation

Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs

Electrical characteristics of three-dimensional SOI/CMOS IC's

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

Scaling fully depleted SOI CMOS

The waveform degradation in VLSI interconnections

SOI design for competitive CMOS VLSI

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Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits

Short-channel effects in SOI MOSFETs

A method for the prediction of hot-carrier lifetime in floating SOI NMOSFETs

Model selection for SOI MOSFET circuit simulation

Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs

Electrical characteristics of three-dimensional SOI/CMOS IC's

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

Scaling fully depleted SOI CMOS

The waveform degradation in VLSI interconnections

SOI design for competitive CMOS VLSI