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Vlsi architectures for computing multiplications and inverses in gf(2-m)
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Shao, H. M. Omura, J. K. Reed, I. S. Wang, C. C. Deutsch, L. J. Truong, T. K. |
| Copyright Year | 1983 |
| Description | Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation. |
| File Size | 2661656 |
| Page Count | 13 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19840005338 |
| Archival Resource Key | ark:/13960/t5k98189x |
| Language | English |
| Publisher Date | 1983-11-15 |
| Access Restriction | Open |
| Subject Keyword | Numerical Analysis Multipliers Algorithms Coding Computer Techniques Very Large Scale Integration Shift Registers Architecture Computers Cryptography Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
