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Parallel subconvolution filtering architectures
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Gray, Andrew A. |
| Copyright Year | 2003 |
| Description | These architectures are based on methods of vector processing and the discrete-Fourier-transform/inverse-discrete- Fourier-transform (DFT-IDFT) overlap-and-save method, combined with time-block separation of digital filters into frequency-domain subfilters implemented by use of sub-convolutions. The parallel-processing method implemented in these architectures enables the use of relatively small DFT-IDFT pairs, while filter tap lengths are theoretically unlimited. The size of a DFT-IDFT pair is determined by the desired reduction in processing rate, rather than on the order of the filter that one seeks to implement. The emphasis in this report is on those aspects of the underlying theory and design rules that promote computational efficiency, parallel processing at reduced data rates, and simplification of the designs of very-large-scale integrated (VLSI) circuits needed to implement high-order filters and correlators. |
| File Size | 81772 |
| Page Count | 1 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20110024118 |
| Archival Resource Key | ark:/13960/t3324wn20 |
| Language | English |
| Publisher Date | 2003-08-01 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Very Large Scale Integration Vector Processing Computers Fourier Transformation Discrete Functions Digital Filters Parallel Processing Computers Ntrs Nasa Technical Reports ServerĀ (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |