Loading...
Please wait, while we are loading the content...
Similar Documents
A 12-bit 150-MHz 1.25- 2mm CMOS DAC
| Content Provider | CiteSeerX |
|---|---|
| Author | He, Yigang Jiang, Jinguang Sun, Yichuang |
| Abstract | This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are r 0.6 LSB and r 0.9 LSB, respectively. The circuit is fabricated in 0.5 mP, two-poly two-metal, 5.0V, mixed-signal CMOS process. It occupies mmmm 96.027.1 u chip area, when operating at 150 MHz and dissipates 91.6mW from a 5.0V power supply, which is much smaller than that of [1]. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Cmos Dac Significant Bit Binary Weighted Array Integral Nonlinearity Power Supply Measured Differential Nonlinearity Chip Area Unary Array Mixed-signal Cmos Process Segmented Architecture Gradient Error |
| Content Type | Text |
| Resource Type | Article |
