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A Single-Chip CMOS Digitally Synthesized 0-35 MHz Agile Function Generator
Content Provider | CiteSeerX |
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Author | Thanachayanont, A. Meenakarn, C. |
Abstract | Abstract: This paper describes the design and implementation of a single-chip digitally synthesized 0-35 MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit onchip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-µm CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm 2 die area and dissipates 0.4 W at 100-MHz clock frequency. 1. |
File Format | |
Access Restriction | Open |
Subject Keyword | Word Resolution Complete Chip Random Waveform On-chip 10-bit Dac 190-ns Frequency Power-down Function 100-mhz Clock Frequency Main Feature Integrated Direct Digital Synthesizer 0233-hz Frequency Step Frequency Modulation 12-bit Phase 0-35 Mhz Agile Function Generator Die Area Cmos Technology Maximum Clock Frequency 10-bit Onchip Digital-to-analog Converter 3-v Supply Voltage 32-bit Frequency |
Content Type | Text |
Resource Type | Article |