NDLI: A 12-b, 150 MHz Sample/s CMOS Current Steering D/A Converter with Gradient Error Compensation

Content Provider	Springer Nature Link
Author	Jiang, Jinguang Wang, Bo Wang, Yaonan
Copyright Year	2006
Abstract	This paper discusses a circuit of 12-b, 150 MHz Sample/s current steering DAC with hierarchical symmetrical switching sequences which will compensate gradient error. The circuit of 12-b DAC employs segmented architecture, the least significant bits (LSB's) steer a binary weighted array, while the most significant bits (MSB's) are thermometer decoded and steer a unary array.The measured differential nonlinearity and integral nonlinearity are ± 0.6 least significant bit (LSB) and ±0.9 LSB, respectively. The output spectrum of the DAC is −63 dB with an input frequency of 30 MHz at 150 MHz conversion rate. The circuit is fabricated in 0.5 μ μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process and occupies 1.27 × 0.96 mm, when operating at 150 MHz Sample/s, it dissipates 91.6 mW from 5.0 V power supply which is much lower than those of [1].
Starting Page	263
Ending Page	273
Page Count	11
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	46
Issue Number	3
e-ISSN	15731979
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2006-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	D/A converter gradient error nonlinearity matching switching sequence thermometer-decoded binary-weighted mixed analog-digital integrated circuit Electronic and Computer Engineering Signal, Image and Speech Processing Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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