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A 12-bit 150-MHz 1 . 25-2 mm CMOS DAC
| Content Provider | Semantic Scholar |
|---|---|
| Author | He, Yigang Jiang, Jinguang Sun, Yichuang |
| Copyright Year | 2001 |
| Abstract | This paper presents a 12-bit 150-MHz current steering DAC with hierarchical symmetrical switching sequence that compensates gradient errors. The circuit of the DAC employs segmented architecture; the least significant bits (LSBs) steer a binary weighted array, while the most significant bits (MSBs) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB and 0.9 LSB, respectively. The circuit is fabricated in 0.5 m , twopoly two-metal, 5.0V, mixed-signal CMOS process. It occupies mm mm 96 . 0 27 . 1 chip area, when operating at 150 MHz and dissipates 91.6mW from a 5.0V power supply, which is much smaller than that of [1]. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://uhra.herts.ac.uk/bitstream/handle/2299/6796/904225.pdf?sequence=1 |
| Alternate Webpage(s) | https://uhra.herts.ac.uk/bitstream/handle/2299/6796/904225.pdf?sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
