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| Content Provider | The American Society of Mechanical Engineers (ASME) Digital Collection |
|---|---|
| Author | Kaisare, Abhijit Agonafer, Dereje Haji-Sheikh, A. Chrysler, Greg Mahajan, Ravi |
| Copyright Year | 2005 |
| Abstract | Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis. |
| Sponsorship | Heat Transfer Division and Electronic and Photonic Packaging Division |
| Starting Page | 675 |
| Ending Page | 682 |
| Page Count | 8 |
| File Format | |
| ISBN | 0791842002 |
| DOI | 10.1115/IPACK2005-73486 |
| e-ISBN | 0791837629 |
| Volume Number | Advances in Electronic Packaging, Parts A, B, and C |
| Conference Proceedings | ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference |
| Language | English |
| Publisher Date | 2005-07-17 |
| Publisher Place | San Francisco, California, USA |
| Access Restriction | Subscribed |
| Subject Keyword | Temperature Finite element methods Separation (technology) Optimization Heat flux Silicon chips Design Finite element model Thermal resistance Energy dissipation Finite element analysis Junctions Clocks |
| Content Type | Text |
| Resource Type | Article |
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