NDLI: Thermal Performance Improvement of Through Silicon Via (TSV) Technology on 3-D Stack Packages

Content Provider	The American Society of Mechanical Engineers (ASME) Digital Collection
Author	Kuo, Wei-Shen Wang, Mingzong Chen, Eason Lai, Jeng-Yuan Wang, Yu-Po
Copyright Year	2008
Abstract	With electronic package tends to be lighter, thinner and smaller, the stacking of the many chips in the 3-D stack packages become more and more popular package. However, the stacking of the multi-function chips in the 3-D stack packages will result in high thermal dissipation. Thermal management has turned into one of the most primary challenge of semiconductor designers. The new technology is required to remove the heat effectively. 3-D stacked package with Through Silicon Via (TSV) technology is developed for two chips in a package. Electrical connections in the silicon interposer are formed by TSV. The silicon interposer has better thermal conductivity than that without interposer, therefore the package thermal resistance is lower. In this paper, thermal evaluations on Flip-Chip Ball Grid Array (FC-BGA) packages were presented using CFD modeling technique. The evaluation topics covered impact of Through Silicon Via (TSV) and dummy bumps, various power consumption, die size and package size effects. Besides, the thermal performance of the package would be decided by thermal conductivity of under fill. Finally, thermal suggestions were concluded for designers to design in TSV arrangements to effectively dissipate hot source.
Starting Page	1523
Ending Page	1526
Page Count	4
File Format	PDF
ISBN	9780791848715
DOI	10.1115/IMECE2008-67240
e-ISBN	9780791838402
Volume Number	Volume 10: Heat Transfer, Fluid Flows, and Thermal Systems, Parts A, B, and C
Conference Proceedings	ASME 2008 International Mechanical Engineering Congress and Exposition
Language	English
Publisher Date	2008-10-31
Publisher Place	Boston, Massachusetts, USA
Access Restriction	Subscribed
Subject Keyword	Fc-bga Cfd Simulation Tsv Semiconductors (materials) Energy consumption Computational fluid dynamics Flip-chip Electronic packages Modeling Design Heat Thermal resistance Ball-grid-array packaging Energy dissipation Thermal conductivity Thermal management Silicon Diluents
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in