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  1. Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
  2. Global interconnections in FPGAs: modeling and performance analysis
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Interconnection lengths and delays estimation for communication links in FPGAs
Timing optimization in logic with interconnect
Multi-core architectures and streaming applications
Parallel vs. serial on-chip communication
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk
The next resource war: computation vs. communication
Efficient tiling patterns for reconfigurable gate arrays
Revisiting fidelity: a case of elmore-based Y-routing trees
Global interconnections in FPGAs: modeling and performance analysis
Sidewinder: a scalable ILP-based router
Rent's rule and parallel programs: characterizing network traffic behavior
Circuit and physical design of the MDGRAPE-4 on-chip network links

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Global interconnections in FPGAs: modeling and performance analysis

Content Provider ACM Digital Library
Author D'Alessandro, Crescenzo Yakovlev, Alex Mak, Terrence Luk, Wayne Cheung, Peter Y. K. Sedcole, Pete
Abstract This paper presents a new model forglobal routings in FPGAs. The irregular interconnections in FPGAs can be generalized as multiple buffered interconnect stages, of which the electrical waveform can be adequately approximated. Based on the model, expressions of delay and fundamental throughput of the interconnections have been derived and validated. They are shown in line with the SPICE and FPGA experimental results. Moreover, the model shows that interconnection throughput can be significantly increased using wave-pipelined signaling instead of the conventional delay-based synchronous approach, as has been demonstrated in our FPGA experiments. We conclude this paper by having a discussion about a strategy to further enhance the interconnect throughput.
Starting Page 51
Ending Page 58
Page Count 8
File Format PDF
ISBN 9781595939180
DOI 10.1145/1353610.1353621
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-04-05
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Wave-pipelined Fpga Interconnection Throughput
Content Type Text
Resource Type Article
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