Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With $RC$ Interconnect

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Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization

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Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

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Generalized delay optimization of resistive interconnections through an extension of logical effort

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Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction

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Unified logical effort- a method for delay evaluation and minimization in logic paths with rc interconnect (2007).

Unified logical effort—a method for delay evaluation and minimization in logic paths with rc interconnect.

1 unified logical effort- a method for delay evaluation and minimization in logic paths with rc interconnect (2006).

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Logical Effort using a Novel Discrete Particle Swarm Optimization algorithm

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