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  1. Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
  2. Interconnection lengths and delays estimation for communication links in FPGAs
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Interconnection lengths and delays estimation for communication links in FPGAs
Timing optimization in logic with interconnect
Multi-core architectures and streaming applications
Parallel vs. serial on-chip communication
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk
The next resource war: computation vs. communication
Efficient tiling patterns for reconfigurable gate arrays
Revisiting fidelity: a case of elmore-based Y-routing trees
Global interconnections in FPGAs: modeling and performance analysis
Sidewinder: a scalable ILP-based router
Rent's rule and parallel programs: characterizing network traffic behavior
Circuit and physical design of the MDGRAPE-4 on-chip network links

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Interconnection lengths and delays estimation for communication links in FPGAs

Content Provider ACM Digital Library
Author Mak, Terrence Luk, Wayne Cheung, Peter Y. K. Sedcole, Pete
Abstract This paper presents a new stochastic model to predictinterconnection lengths of communication links in FPGAs. Based on a stochastic inter-module routing model, expected length and variance of interconnections have been rigorously derived and, thus, delay can be computed based on the length estimate. The theoretical results are compared with experimental results of lengths and delays, which are obtained from implementations of links circuits in an FPGA. The stochastic model provides an accurate prediction of length with an average error of 6.3%. Results also show that theproposed model produces reliable predictions of delay and therefore the methodology can be applied to early stage planning and design optimization for communication links. Moreover, as a byproduct of this work, we also present in this paper an interesting phenomenon which we term "interconnection fringing". The fringing effect is attributed to the competition for routing resources in a communication link and will lengthen interconnections and, therefore, increase the delay.
Starting Page 1
Ending Page 10
Page Count 10
File Format PDF
ISBN 9781595939180
DOI 10.1145/1353610.1353612
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-04-05
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Fpga Communciation link Interconnection length prediction
Content Type Text
Resource Type Article
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