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  1. Proceedings of the 2008 international workshop on System level interconnect prediction (SLIP '08)
  2. Revisiting fidelity: a case of elmore-based Y-routing trees
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Interconnection lengths and delays estimation for communication links in FPGAs
Timing optimization in logic with interconnect
Multi-core architectures and streaming applications
Parallel vs. serial on-chip communication
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk
The next resource war: computation vs. communication
Efficient tiling patterns for reconfigurable gate arrays
Revisiting fidelity: a case of elmore-based Y-routing trees
Global interconnections in FPGAs: modeling and performance analysis
Sidewinder: a scalable ILP-based router
Rent's rule and parallel programs: characterizing network traffic behavior
Circuit and physical design of the MDGRAPE-4 on-chip network links

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Revisiting fidelity: a case of elmore-based Y-routing trees

Content Provider ACM Digital Library
Author Rahaman, Hafizur Dasgupta, Parthasarathi Ghosal, Prasun Samanta, Tuhina
Abstract The dominance of interconnect delay in VLSI circuit design is well-known. Construction of routing trees in recent times has to take care of the timing issues for faster design convergence. Thus there is immense scope of research in design and performance of interconnects. Our current work encompasses two aspects of this research. On one hand, we consider the construction of cost-effective global routing trees with the recently introduced Y-interconnects, and on the other hand, we utilize this framework for verifying the supremacy of the Elmore delay estimate for its high fidelity. In order to ensure accurate computation of fidelity, (i) we propose new statistically proven formulae for fidelity, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on several randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of Elmore delay over that of linear delay.
Starting Page 27
Ending Page 34
Page Count 8
File Format PDF
ISBN 9781595939180
DOI 10.1145/1353610.1353616
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-04-05
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Steiner trees Fidelity Rank correlation Routing
Content Type Text
Resource Type Article
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