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  1. Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC '12)
  2. Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis
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Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis
Rank idle time prediction driven last-level cache writeback
Parallel memory defragmentation on a GPU
A higher order theory of locality
Can parallel data structures rely on automatic memory managers?
Can seqlocks get along with programming language memory models?
Trace-driven simulation of memory system scheduling in multithread application
Analysis of pure methods using garbage collection
Supporting virtual memory in GPGPU without supporting precise exceptions
Towards region-based memory management for Go
A study towards optimal data layout for GPU computing
Design space exploration of memory model for heterogeneous computing
Defensive loop tiling for multi-core processor

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Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis

Content Provider ACM Digital Library
Author Wu, Meng-Ju Yeung, Donald
Abstract Understanding multicore memory behavior is crucial, but can be challenging due to the complex cache hierarchies employed in modern CPUs. In today's hierarchies, performance is determined by complicated thread interactions, such as interference in shared caches and replication and communication in private caches. Researchers normally perform extensive simulations to study these interactions, but this can be costly and not very insightful. An alternative is multicore reuse distance (RD) analysis, which can provide extremely rich information about multicore memory behavior. In this paper, we apply multicore RD analysis to better understand cache system design. We focus on loop-based parallel programs, an important class of programs for which RD analysis provides high accuracy. We propose a novel framework to identify optimal multicore cache hierarchies, and extract several new insights. We also characterize how the optimal cache hierarchies vary with core count and problem size.
Starting Page 2
Ending Page 11
Page Count 10
File Format PDF
ISBN 9781450312196
DOI 10.1145/2247684.2247687
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2012-06-16
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Reuse distance Cache performance Chip multiprocessors
Content Type Text
Resource Type Article
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