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  1. Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC '12)
  2. Rank idle time prediction driven last-level cache writeback
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Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis
Rank idle time prediction driven last-level cache writeback
Parallel memory defragmentation on a GPU
A higher order theory of locality
Can parallel data structures rely on automatic memory managers?
Can seqlocks get along with programming language memory models?
Trace-driven simulation of memory system scheduling in multithread application
Analysis of pure methods using garbage collection
Supporting virtual memory in GPGPU without supporting precise exceptions
Towards region-based memory management for Go
A study towards optimal data layout for GPU computing
Design space exploration of memory model for heterogeneous computing
Defensive loop tiling for multi-core processor

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Rank idle time prediction driven last-level cache writeback

Content Provider ACM Digital Library
Author Wang, Zhe Jiménez, Daniel A. Khan, Samira M.
Abstract In modern DDRx memory systems, memory write requests can cause significant performance loss by increasing the memory access latency for subsequent read requests targeting the same device. In this paper, we propose a rank idle time prediction driven last-level cache writeback technique. This technique uses a rank idle time predictor to predict long phases of idle rank cycles. The scheduled dirty cache blocks generated from last-level cache are written back during the predicted long idle rank period. This technique allows servicing write request at the point that minimize the delay it caused to the following read requests. Write-induced interference can be significantly reduced by using our technique. We evaluate our technique using cycle-accurate full-system simulator and SPEC CPU2006 benchmarks. The results shows the technique improves performance in an eight-core system with memory-intensive workloads on average by 10.5% and 10.1% over conventional writeback using two-rank and four-rank DRAM configurations respectively.
Starting Page 21
Ending Page 29
Page Count 9
File Format PDF
ISBN 9781450312196
DOI 10.1145/2247684.2247690
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2012-06-16
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Llc Writeback Memory management
Content Type Text
Resource Type Article
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